Semiconductor nanowires are becoming a research focus in nanotechnology. Various methods of forming metal-oxide-semiconductor field-effect transistors (MOSFETs) comprising nanowires have been explored, including the use of dual material nanowire, where different material nanowires are used for N-channel field-effect transistor (NFET) and P-channel field-effect transistor (PFET) devices. For example, silicon (Si) nanowires may be used as the channel material for the NFET devices, while silicon germanium (SiGe) nanowires may be used as the channel material for the PFET devices. As another example, multiple-stacked (“multi-stack”) nanowires have been used in forming NFET and PFET devices, increasing the current carrying capability of these devices. One of the multi-stack candidates is the FET. A trigate FET device consists of a vertical standing Si body (fin) and the gate is wrapped around either side creating two channels on the sides and one on the top. High-aspect-ratio trigate FETs with aggressively scaled fin widths (30 nm and narrower) are of particular interest as they combine excellent short channel effect (SCE) immunity with high drivability per unit chip area.